Encoding:

Format:

ADDU[_S].PH 

ADDU.PH   rd, rs, rt

ADDU_S.PH rd, rs, rt

Purpose:

Unsigned Add Integer Halfwords

Add two pairs of unsigned integer halfwords, with optional saturation.

Description:

rd = sign_extend(sat16(rs31..16 + rt31..16) || sat16(rs15..0 + rt15..0))

The two right-most unsigned integer halfword elements in register rt are added to the corresponding unsigned integer halfword elements in register rs.

For the non-saturating version of the instruction, the result modulo 65,536 is written into the corresponding element in register rd.

For the saturating version of the instruction, the addition is performed using unsigned saturating arithmetic. Results that overflow are clamped to the largest representable value (65,535 decimal, 0xFFFF hexadecimal) before being written to the destination register rd.

Bit 31 of the result is extended into the 32 most-significant bits of the destination register.

For either instruction, if any of the individual additions result in overflow or saturation, a 1 is written to bit 20 in the

DSPControl register within the ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDU.PH:
   tempB15..0 = addU16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = addU16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
ADDU_S.PH:
   tempB15..0 = satAddU16( GPR[rs]31..16 , GPR[rt]31..16 )
   tempA15..0 = satAddU16( GPR[rs]15..0 , GPR[rt]15..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled